Espressif Systems /ESP32-C3 /SPI2 /MISC

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Interpret as MISC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CS0_DIS)CS0_DIS 0 (CS1_DIS)CS1_DIS 0 (CS2_DIS)CS2_DIS 0 (CS3_DIS)CS3_DIS 0 (CS4_DIS)CS4_DIS 0 (CS5_DIS)CS5_DIS 0 (CK_DIS)CK_DIS 0MASTER_CS_POL 0 (SLAVE_CS_POL)SLAVE_CS_POL 0 (CK_IDLE_EDGE)CK_IDLE_EDGE 0 (CS_KEEP_ACTIVE)CS_KEEP_ACTIVE 0 (QUAD_DIN_PIN_SWAP)QUAD_DIN_PIN_SWAP

Description

SPI misc register

Fields

CS0_DIS

SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.

CS1_DIS

SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.

CS2_DIS

SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.

CS3_DIS

SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.

CS4_DIS

SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.

CS5_DIS

SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.

CK_DIS

1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.

MASTER_CS_POL

In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.

SLAVE_CS_POL

spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.

CK_IDLE_EDGE

1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.

CS_KEEP_ACTIVE

spi cs line keep low when the bit is set. Can be configured in CONF state.

QUAD_DIN_PIN_SWAP

1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.

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